3D heterogeneous integration of high performance high-K metal gate GaN NMOS and Si PMOS transistors on 300mm high-resistivity Si substrate for energy-efficient and compact power delivery, RF (5G and beyond) and SoC applications

Abstract

We have demonstrated industry’s first 300mm 3D heterogeneous integration of high performance, low-leakage high-K dielectric metal gate enhancement-mode (e-mode) GaN NMOS and Si PMOS transistors on 300mm high-resistivity (HR) Si(111) substrate, enabled by 300mm GaN MOCVD epitaxy and 300mm 3D layer transfer. The fabricated (bottom device layer) high-K dielectric e-mode GaN NMOS transistors, integrated on a 300mm HR Si(111) substrate, show excellent electrical characteristics and figure-of-merits (FOM) for realizing energy-efficient, compact voltage regulators and RF front-end components such as power amplifiers, low-noise amplifiers and RF switches, with (i) I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</inf> as low as 100pA/μm (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</inf> =5V, V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> =0V), (ii) high I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D,max</inf> =1.5mA/μm; (iii) R <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf> as low as 610Ω-μm, significantly better than industry-standard Si transistors at equivalent drain breakdown (BV <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</inf> ), (iv) excellent RF performance: f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> =190GHz, f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAX</inf> =300GHz, PAE=56% at mmwave frequency (f=28GHz), and PAE=70% at sub-7GHz (f=5GHz), significantly better than industry-standard GaAs and Si RF transistors, (v) excellent RF switch FOM, R <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</inf> C <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</inf> =110fs, and (vi) low noise figure, NF <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</inf> =1.36dB (f=28GHz), 0.4dB (f=5GHz) and 0.27dB (f=1.8GHz), all at SoC-compatible voltages. The fabricated (top device layer) L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> =65nm and 130nm Si PMOS transistors, which are monolithically integrated on top of the bottom GaN NMOS transistors by 300mm 3D layer transfer, show respectively, high drive current of 0.85mA/μm, and low I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</inf> of 150pA/μm at V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</inf> =-1.2V. Such a monolithic 3D integration of GaN NMOS and Si PMOS enables full integration of energy-efficient, truly compact power delivery and RF solutions with CMOS digital signal processing, logic computation and control, memory functions and analog circuitries for next generation power delivery, RF (5G and beyond) and SoC applications.