M. Hattendorf

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

K. Mistry, R. Chau, Changhwan Choi et al. · 2007 · 825 citations

Nm Logic Technology, Engineering, Vlsi Design +18

A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

C. Auth, C. Allen, A. Blattner et al. · 2012 · 749 citations

Low-power Cmos Technology, Engineering, Vlsi Design +19

A 10nm high performance and low-power CMOS technology featuring 3^rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects

C. Auth, A. Aliyarukunju, M. Asoro et al. · 2017 · 353 citations

Engineering, Integrated Circuits, High Performance +18

45nm High-k + metal gate strain-enhanced transistors

C. Auth, A. Cappellani, Jang‐Soo Chun et al. · 2008 · 204 citations

Materials Engineering, Electrical Engineering, Engineering +11

Intrinsic transistor reliability improvements from 22nm tri-gate technology

S. Ramey, A. Ashutosh, C. Auth et al. · 2013 · 166 citations

Reliability, Electrical Engineering, Reliability Engineering +14