K. Kurumada - Concepedia

Author

K. Kurumada

NTT (Japan)

Also Known As

K Kurumada, K. Kurumada, Katsuhiko Kurumada

Publications

406

Citations

H-Index

Concepts

All Affiliations

NTT (Japan)Musashino Academia Musicae NTT Basic Research Laboratories

About

K. Kurumada is an author at NTT (Japan) specializing in applied physics, engineering, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	9	9	231
2	Applied Physics	9	9	231
3	Electrical Engineering	7	7	188
4	Chemistry	1	1	10
5	Materials Science	1	1	10

K. Kurumada

Publications

314

Citations

H-Index

Page 1

	Year	Citations
Self-align implantation for <i>n</i> <sup>+</sup> -layer technology (SAINT) for high-speed GaAs ICs K. Yamasaki, K. Asai, T. Mizutani, Electronics Letters	1982	72
Observation of Room Temperature Current Oscillation in InGaAs/InAlAs MQW Pin Diodes Yuichi Kawamura, Koichi Wakita, H. Asahi, Japanese Journal of Applied Physics Room TemperatureElectrical EngineeringEngineeringPhysicsQuantum Device	1986	55
GaAs LSI-directed MESFET's with self-aligned implantation for n<sup>+</sup>-layer technology (SAINT) K. Yamasaki, K. Asai, K. Kurumada IEEE Transactions on Electron Devices SemiconductorsSemiconductor TechnologyElectrical EngineeringEngineeringNanoelectronics	1982	50
Facet oxidation of InGaAs/GaAs strained quantum-well lasers M. Okayasu, Mitsuo Fukuda, Tatsuya Takeshita, Journal of Applied Physics PhotonicsEngineeringPhysicsFacet OxidationApplied Physics	1991	33
Ion-implanted E/D-type GaAs IC technology Takashi Furutsuka, T. Tsuji, F. Katano, Electronics Letters Semiconductor TechnologyElectrical EngineeringIon ImplantationEngineeringElectronic Engineering	1981	28
Below 20 ps/gate operation with GaAs SAINT FETs at room temperature K. Yamasaki, Y. Yamane, K. Kurumada Electronics Letters Semiconductor TechnologyRoom TemperatureElectrical EngineeringEngineeringPhysics	1982	20
Planar InGaAs/InP PINFET fabricated by Be ion implantation Satoshi Hata, M. Ikeda, Toshimasa Amano, Electronics Letters EngineeringOptoelectronic DevicesPlanar Ingaas/inp PinfetSemiconductor DeviceSemiconductors	1984	13
GaAs planar Gunn digital devices by sulphur-ion implantation T. Mizutani, K. Kurumada Electronics Letters Electrical EngineeringEngineeringSchottky-barrier-gate Gunn-effect DevicesRf SemiconductorSulphur-ion Implantation	1975	12
High-power SLM operation of 1.3 μm InP/InGaAsP DFB LD with doubly buried heterostructure on <i>p</i> -type InP substrate Y. Suzuki, Haruo Nagai, Y. Noguchi, Electronics Letters	1984	11
Threshold voltage margin of normally-off GaAs MESFET in DCFL circuit M. Ino, K. Kurumada, M. Ohmori IEEE Electron Device Letters Device ModelingElectrical EngineeringSemiconductor DeviceEngineeringElectronic Engineering	1981	10

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