N. Nakamura

A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro

Koichi Takeda, Y. Aimoto, N. Nakamura et al. · IEEE Journal of Solid-State Circuits · 2000 · 66 citations

Low-power Electronics, Electrical Engineering, Engineering +8

High-level synthesis challenges and solutions for a dynamically reconfigurable processor

Takao Toi, N. Nakamura, Yoshinosuke Kato et al. · Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design · 2006 · 52 citations

Engineering, Reconfigurable Processor, Computer Architecture +17

A loadless CMOS four-transistor SRAM cell in a 0.18-μm logic technology

K. Noda, K. Matsui, Koichi Takeda et al. · IEEE Transactions on Electron Devices · 2001 · 46 citations

Low-power Electronics, High Density, Electrical Engineering +12

New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications

Tarô Fujii, Takao Toi, Teruhito Tanaka et al. · 2018 · 30 citations

Artificial Intelligence, Engineering, Computer Architecture +17

An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield

K. Noda, Koichi Takeda, K. Matsui et al. · IEEE Journal of Solid-State Circuits · 2001 · 22 citations

Non-volatile Memory, Electrical Engineering, Engineering +12