A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro

Koichi Takeda, Y. Aimoto, N. Nakamura, +10

IEEE Journal of Solid-State Circuits

Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignVlsi Architecture +6

High-level synthesis challenges and solutions for a dynamically reconfigurable processor

Takao Toi, N. Nakamura, Yoshinosuke Kato, +3

Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design

EngineeringReconfigurable ProcessorComputer ArchitectureSystem SynthesisDrp Architecture +15

A loadless CMOS four-transistor SRAM cell in a 0.18-μm logic technology

K. Noda, K. Matsui, Koichi Takeda, +1

IEEE Transactions on Electron Devices

Low-power ElectronicsHigh DensityElectrical EngineeringNon-volatile MemoryLoadless Cmos Four-transistor +10

New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications

Tarô Fujii, Takao Toi, Teruhito Tanaka, +6

Artificial IntelligenceEngineeringComputer ArchitectureIntelligent SystemsEmbedded Systems +15

An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield

K. Noda, Koichi Takeda, K. Matsui, +8

IEEE Journal of Solid-State Circuits

Non-volatile MemoryElectrical EngineeringEngineeringVlsi DesignLoadless Four-transistor +10

64 Mb 6.8 ns random ROW access DRAM macro for ASICs

T. Kimuta, K. Takeda, Y. Aimoto, +8

Hardware SecurityMemory ArchitectureEngineeringEdge ComputingHigh-performance Architecture +12

Optimizing time and space multiplexed computation in a dynamically reconfigurable processor

Takao Toi, N. Nakamura, Tarô Fujii, +4

EngineeringReconfigurable ProcessorComputer ArchitectureState Transition ControllerProcessor Architecture +14

Constructing a Human-like agent for the Werewolf Game using a psychological model based multiple perspectives

N. Nakamura, Michimasa Inaba, Keníchi Takahashi, +4

A cost-conscious 32nm CMOS platform technology with advanced single exposure lithography and gate-first metal gate/high-k process

Shunsuke Hasegawa, Y. Kitamura, Kazuo Takahata, +53

Total CostEngineeringVlsi DesignComputer ArchitectureIntegrated Circuits +14

High-level Synthesis Challenges for Mapping a Complete Program on a Dynamically Reconfigurable Processor

Takao Toi, N. Nakamura, Yoshinosuke Kato, +2

IPSJ Transactions on System and LSI Design Methodology