IEEE Journal of Solid-State Circuits · 2000 · 66 citations · 4 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsVlsi DesignCmos Circuit DesignDynamic Power ReductionIntegrated Circuit DesignMemory Subsystem DesignMicroarchitecture DesignTiming AnalysisCmos Logic CircuitsCmos Logic DesignData RetentionData Retention ManagementHigh-speed Cmos DesignLow-power Cmos DesignLow-voltage Cmos DesignMemory Circuit Design
We have used a 5-metal 0.18-/spl mu/m CMOS logic process to develop a 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro. The macro contains: (1) end-point dual-pulse drivers for accurate timing control; (2) a wordline-voltage-level compensation circuit for stable data retention; and (3) an all-adjoining twisted bitline scheme for reduced bitline coupling capacitance. The macro is capable of 400-MHz high-speed access at 1.8-V supply voltage and is 66% the size of a conventional six-transistor SRAM macro. We have also developed a higher-performance 500-MHz loadless four-transistor SRAM macro in a CMOS process using 0.13-/spl mu/m gate length.
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A 1.4 ns access 700 MHz 288 kb SRAM macro with expandable architecture
Haruo Shimizu, K. Ijitsu, H. Akiyoshi et al. · 2003 · 13 citations