New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications

Abstract

We have developed 3rd generation DRP, dynamically reconfigurable processor, for accelerating deep neural networks (DNNs) in embedded micro-processor systems. A DRP unit (supporting 16b FP from this generation) and a newly designed multiply-and-accumulate (MAC) unit are tightly integrated into an STP-3 AI core to achieve high versatility, high performance, and low latency DNN processing. The core also features narrow bit-width streaming data exchange mechanism between the two units. Not only basic 16b FP but also binarized DNN inference computations are supported.