Jami Wiedemer

A 14nm logic technology featuring 2<sup>nd</sup>-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm<sup>2</sup> SRAM cell size

S. Natarajan, M. Agostinelli, Sheikh A. Akbar et al. · 2014 · 532 citations

Engineering, Computer Engineering, Electrical Engineering +16

45nm High-k + metal gate strain-enhanced transistors

C. Auth, A. Cappellani, Jang‐Soo Chun et al. · 2008 · 204 citations

Engineering, Computer Engineering, Electrical Engineering +17

BTI reliability of 45 nm high-K + metal-gate process technology

Sangwoo Pae, M. Agostinelli, M. Brazier et al. · 2008 · 131 citations

Engineering, Electrical Engineering, Materials Science +17

Demonstration of a Stacked CMOS Inverter at 60nm Gate Pitch with Power Via and Direct Backside Device Contacts

M. Radosavljević, ChingYao Huang, Rohit Galatage et al. · 2023 · 32 citations

Engineering, Electrical Engineering, Electronic Materials +15

A 23.6-Mb/mm<inline-formula> <tex-math notation="LaTeX">$^{2}$ </tex-math> </inline-formula> SRAM in 10-nm FinFET Technology With Pulsed-pMOS TVC and Stepped-WL for Low-Voltage Applications

Zheng Guo, Daeyeon Kim, Satyanand Nalam et al. · IEEE Journal of Solid-State Circuits · 2018 · 28 citations

Engineering, Computer Engineering, Electrical Engineering +10