D. Bergstrom

A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

K. Mistry, R. Chau, Changhwan Choi et al. · 2007 · 829 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

C. Auth, C. Allen, A. Blattner et al. · 2012 · 758 citations

Engineering, Computer Engineering, Electrical Engineering +16

Development of preferred orientation in polycrystalline TiN layers grown by ultrahigh vacuum reactive magnetron sputtering

J. E. Greene, J.‐E. Sundgren, Lars Hultman et al. · Applied Physics Letters · 1995 · 395 citations

Natural Sciences, Materials Engineering, Materials Science +15

A 10nm high performance and low-power CMOS technology featuring 3^rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects

C. Auth, A. Aliyarukunju, M. Asoro et al. · 2017 · 369 citations

Engineering, Computer Engineering, Electrical Engineering +17

High performance 32nm logic technology featuring 2<sup>nd</sup> generation high-k + metal gate transistors

P. Packan, Sheikh A. Akbar, M Armstrong et al. · 2009 · 187 citations

Engineering, Computer Engineering, Electrical Engineering +12