S. Lane

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

E. Leobandung, H. Nayakama, D. Mocuta et al. · 2005 · 65 citations

Engineering, Computer Engineering, Electrical Engineering +17

Investigation of CVD SiCOH low-k time-dependent dielectric breakdown at 65nm node technology

F. Chen, Kaushik Chanda, Inderbir S. Gill et al. · 2005 · 42 citations

Engineering, Electrical Engineering, Materials Science +17

Comprehensive reliability evaluation of a 90 nm CMOS technology with Cu/PECVD low-k BEOL

D. Edelstein, H. Rathore, C. Davis et al. · 2004 · 23 citations

Engineering, Electrical Engineering, Materials Science +17

Low temperature inorganic chemical vapor deposition of Ti–Si–N diffusion barrier liners for gigascale copper interconnect applications

Eric Eisenbraun, A. Upham, Raj Kishora Dash et al. · Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena · 2000 · 20 citations · Full text

Engineering, Materials Engineering, Materials Science +17

Reliability, yield, and performance of a 90 nm SOI/Cu/SiCOH technology

D. Edelstein, C. Davis, L. A. Clevenger et al. · 2004 · 18 citations

Engineering, Electrical Engineering, Materials Engineering +16