Byong-Tae Chung

25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV

Dong Uk Lee, Kyung Whan Kim, Kwan Weon Kim et al. · 2014 · 247 citations

Engineering, Computer Engineering, Computer Science +11

A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces

Hyun-Woo Lee, Hoon Choi, Beomju Shin et al. · IEEE Journal of Solid-State Circuits · 2012 · 26 citations

Engineering, Computer Engineering, Computer Science +15

A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology

Hyun-Woo Lee, Ki-Han Kim, Young-Kyoung Choi et al. · IEEE Journal of Solid-State Circuits · 2011 · 23 citations

Engineering, Computer Engineering, Electrical Engineering +17

Sense amplifier with offset mismatch calibration for sub 1-V DRAM core operation

Jinyeong Moon, Byong-Tae Chung · 2010 · 20 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture

Kibong Koo, Sunghwa Ok, Yong-Gu Kang et al. · 2012 · 17 citations

Engineering, Computer Engineering, Electrical Engineering +14