Ivan Siu-Chuang Lu

A 28-nm 75-fs_rms Analog Fractional-$N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction

Wanghua Wu, Chih-Wei Yao, Kunal Godbole et al. · IEEE Journal of Solid-State Circuits · 2019 · 183 citations

Pll Architecture, Integrated Phase Noise, Engineering +13

A SAW-Less GSM/GPRS/EDGE Receiver Embedded in 65-nm SoC

Chi-Yao Yu, Ivan Siu-Chuang Lu, Yen-Horng Chen et al. · IEEE Journal of Solid-State Circuits · 2011 · 37 citations

Low-power Electronics, Electrical Engineering, Quad-band Gsm/gprs/edge Receiver +14

A SAW-less GSM/GPRS/EDGE receiver embedded in a 65nm CMOS SoC

Ivan Siu-Chuang Lu, Chi-Yao Yu, Yen-horng Chen et al. · 2011 · 25 citations

Low-power Electronics, System On Chip, Electrical Engineering +9

A 17.3-mW 0.46-mm2 26/28/39GHz Phased-Array Receiver Front-End with an I/Q-Current-Shared Active Phase Shifter for 5G User Equipment

Xiaohua Yu, Ajaypat Jain, Amitoj Singh et al. · 2021 · 17 citations

17.3-Mw 0.46-Mm2 26/28/39Ghz, Phased-array Receiver Front-end, Millimeter Wave Technology +9

ADC precision requirement for digital ultra-wideband receivers with sublinear front-ends: a power and performance perspective

Ivan Siu-Chuang Lu, Neil Weste, Sri Parameswaran · 2006 · 12 citations

Engineering, Performance Perspective, Analog-to-digital Converter +11