A 5G FR2 Power-Amplifier With an Integrated Power-Detector for Closed-Loop EIRP Control

Abstract

A fifth-generation (5G) frequency range 2 (FR2) transmitter front end with a fully integrated power detector for enabling closed-loop power control is presented. The power detection path includes a miniature broad-side directional coupler, a sense pair, and a current-mode successive approximation analog-to-digital converter. The stacked power amplifier (PA) implemented in a 28-nm CMOS silicon on insulator (SOI) process delivers 12.5-dBm output power with a power-added efficiency of 10% and an error vector magnitude (EVM) lower than −25 dB with a CP-OFDM/64-QAM/400-MHz bandwidth signal. The PA supports 5G frequency bands n257/n258/n261 covering a frequency range from 24.25 to 29.5 GHz. With a matched output load, the power detector has less than ±0.15-dB error over a 15-dB power dynamic range and 85° temperature range.