Hsien-Ching Lo

Source/drain eSiGe engineering for FinFET technology

Jianwei Peng, Yi Qi, Hsien-Ching Lo et al. · Semiconductor Science and Technology · 2017 · 17 citations

Materials Science, Electrical Engineering, Epitaxial Growth +12

A 12nm FinFET Technology Featuring 2nd Generation FinFET for Low Power and High Performance Applications

Hsien-Ching Lo, Dae Hee Choi, Yue Hu et al. · 2018 · 16 citations

Low-power Electronics, Low Power, Electrical Engineering +10

In-Situ Boron Doped SiGe Epitaxy Optimization for FinFET Source/Drain

Yi Qi, Jianwei Peng, Hsien-Ching Lo et al. · ECS Transactions · 2016 · 14 citations

Materials Engineering, Electrical Engineering, Engineering +10

Effects of high in-situ source/drain boron doping in p-FinFETs on physical and device performance characteristics

Shashidhar Shintri, Chloe Yong, Baofu Zhu et al. · Materials Science in Semiconductor Processing · 2018 · 14 citations

Device Performance Characteristics, Electrical Engineering, Engineering +7

45nm SOI CMOS Technology with 3X hole mobility enhancement and Asymmetric transistor for high performance CPU application

Samuel Fung, Hsien-Ching Lo, Chun-Kai Cheng et al. · 2007 · 11 citations

Thin Film Soi, Engineering, Vlsi Design +18