Jer-Yi Lin

Junctionless Nanosheet (3 nm) Poly-Si TFT: Electrical Characteristics and Superior Positive Gate Bias Stress Reliability

Jer-Yi Lin, Malkundi Puttaveerappa Vijay Kumar, Tien‐Sheng Chao · IEEE Electron Device Letters · 2017 · 21 citations

Materials Science, Electrical Characteristics, Electrical Engineering +15

Junctionless Poly-Si Nanowire Transistors With Low-Temperature Trimming Process for Monolithic 3-D IC Application

Jer-Yi Lin, Po‐Yi Kuo, Ko-Li Lin et al. · IEEE Transactions on Electron Devices · 2016 · 20 citations

Engineering, Integrated Circuits, Silicon On Insulator +19

High-Performance Pi-Gate Poly-Si Junctionless and Inversion Mode FET

Dong‐Ru Hsieh, Jer-Yi Lin, Po‐Yi Kuo et al. · IEEE Transactions on Electron Devices · 2016 · 17 citations

Electrical Engineering, Engineering, Microfabrication +12

Vertically Stacked Cantilever n-Type Poly-Si Junctionless Nanowire Transistor and Its Series Resistance Limit

Chun-Chih Chung, Chiuan-Huei Shen, Jer-Yi Lin et al. · IEEE Transactions on Electron Devices · 2017 · 17 citations

Series Resistance Limit, Electrical Engineering, Engineering +15

Impact of Crystallization Method on Poly-Si Tunnel FETs

Yi-Hsuan Chen, William Cheng-Yu, Jer-Yi Lin et al. · IEEE Electron Device Letters · 2015 · 14 citations

Engineering, Integrated Circuits, Silicon On Insulator +17