Anisur Rahman

Theory of ballistic nanotransistors

Anisur Rahman, Jing Guo, Supriyo Datta et al. · IEEE Transactions on Electron Devices · 2003 · 769 citations

Engineering, Semiconductor Device, Nanoelectronics +16

A 10nm high performance and low-power CMOS technology featuring 3^rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects

C. Auth, A. Aliyarukunju, M. Asoro et al. · 2017 · 353 citations

Engineering, Integrated Circuits, High Performance +18

A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications

C.-H. Jan, Uma Bhattacharya, R. Brain et al. · 2012 · 303 citations

Engineering, Vlsi Design, Computer Architecture +18

A compact scattering model for the nanoscale double-gate MOSFET

Anisur Rahman, Mark Lundstrom · IEEE Transactions on Electron Devices · 2002 · 192 citations

Device Modeling, Electrical Engineering, Nanoscale System +15

On the Validity of the Parabolic Effective-Mass Approximation for the I–V Calculation of Silicon Nanowire Transistors

Jun Wang, Anisur Rahman, Arnab Ghosh et al. · IEEE Transactions on Electron Devices · 2005 · 189 citations · Full text