Roberto Nonis

A 23-GHz Low-Phase-Noise Digital Bang–Bang PLL for Fast Triangular and Sawtooth Chirp Modulation

Dmytro Cherniak, Luigi Grimaldi, Luca Bertulessi et al. · IEEE Journal of Solid-State Circuits · 2018 · 80 citations · Full text

Radio Frequency, High-frequency Device, Mixed-signal Integrated Circuit +8

A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS

Werner Grollitsch, Roberto Nonis, Nicola Da Dalt · 2010 · 71 citations

Electrical Engineering, Engineering, Art Digital Plls +11

A Design Methodology for MOS Current-Mode Logic Frequency Dividers

Roberto Nonis, E. Palumbo, Pierpaolo Palestri et al. · IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · 2007 · 64 citations · Full text

Electrical Engineering, Circuit Parameters, Hand Calculations +13

digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture

Roberto Nonis, Werner Grollitsch, Thomas Santa et al. · IEEE Journal of Solid-State Circuits · 2013 · 63 citations

Hardware Security, Low Jitter, Engineering +14

Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture

Roberto Nonis, Nicola Da Dalt, Pierpaolo Palestri et al. · IEEE Journal of Solid-State Circuits · 2005 · 61 citations · Full text

Lc-vco Pll, New Low-jitter Analog, Vlsi Design +8