A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS

Abstract

State of the art digital PLLs can be divided in two categories, depending on the implementation of the digital phase detector. Digital clocking and wireline applications mostly use a Bang-Bang detector (BBPLLs) [1–3], offering very low jitter values in integer-N mode but not supporting fractional-N synthesis, which is desirable to implement, i.e., spread spectrum clocking (SSC) for EMI reductions. Wireless applications implement time to digital converters (TDC) [4–6] which allow fractional-N synthesis, but require high architecture complexity, need calibration routines for period normalization, and introduce analog limitations that a digital PLL should be intended to eliminate.