Dmytro Cherniak

A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-<i>N</i> Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking

Alessio Santiccioli, Mario Mercandelli, Luca Bertulessi et al. · IEEE Journal of Solid-State Circuits · 2020 · 84 citations

Fast Lock, Radio Frequency, Phase-locked Loop +11

A 23-GHz Low-Phase-Noise Digital Bang–Bang PLL for Fast Triangular and Sawtooth Chirp Modulation

Dmytro Cherniak, Luigi Grimaldi, Luca Bertulessi et al. · IEEE Journal of Solid-State Circuits · 2018 · 80 citations · Full text

Radio Frequency, High-frequency Device, Mixed-signal Integrated Circuit +8

digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture

Roberto Nonis, Werner Grollitsch, Thomas Santa et al. · IEEE Journal of Solid-State Circuits · 2013 · 63 citations

Hardware Security, Low Jitter, Engineering +14

A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter

Mario Mercandelli, Alessio Santiccioli, Angelo Parisi et al. · IEEE Journal of Solid-State Circuits · 2021 · 58 citations

Main Pll Operation, Conventional Type-i Pll, High-frequency Device +7

A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range

Luca Bertulessi, Luigi Grimaldi, Dmytro Cherniak et al. · 2018 · 49 citations

Fast Lock, Electrical Engineering, Engineering +11