digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture

Abstract

This paper introduces a novel architecture of digital PLL. The goal of this architecture is to reach low jitter, fractional operation, and FSK modulation capability with low architecture complexity for small area, low power, and minimal design effort. The architecture is based on the bang-bang phase detector, so that usage of time-to-digital-converter circuits is avoided, with no need for any background calibration. The key enabling blocks are a phase interpolator-based exact fractional frequency divider, and a multi-output bang-bang phase detector. The prototype implemented in 130 nm reaches 1-ps <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> absolute jitter while operating in integer mode and 1.9 ps <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> absolute jitter while operating in full fractional mode, with an output frequency of 1 GHz and reference frequency of 25 MHz, consuming 7.4 mW from a supply of 1.3 V. FSK modulation of the 1 GHz carrier up to 300 kbps with a frequency deviation of ±150 kHz is also implemented and measured .