R.P. Havreluk

A High-Speed 128-kb MRAM Core for Future Universal Memory Applications

J. DeBrosse, D. Gogl, Ann-Christin Bette et al. · IEEE Journal of Solid-State Circuits · 2004 · 63 citations

Engineering, Computer Engineering, Electrical Engineering +11

A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier

J. Barth, W. Reohr, P. Parries et al. · IEEE Journal of Solid-State Circuits · 2008 · 60 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier

J. Barth, W. Reohr, P. Parries et al. · 2007 · 35 citations

Engineering, Computer Engineering, Electrical Engineering +14

A high-speed 128 Kbit MRAM core for future universal memory applications

Ann-Christin Bette, J. DeBrosse, D. Gogl et al. · 2004 · 25 citations

Engineering, Computer Engineering, Electrical Engineering +9

An 18 ns 56-bit multiply-adder circuit

Robert K. Montoye, Peter W. Cook, E. Hökenek et al. · 1990 · 14 citations

Engineering, Computer Engineering, Computer Science +15