André Hiess

Atomic layer deposition for high aspect ratio through silicon vias

Martin Knaut, Marcel Junige, Volker Neumann et al. · Microelectronic Engineering · 2013 · 43 citations

Materials Science, Wafer Scale Processing, Engineering +10

Plasma Etching of Tapered Features in Silicon for MEMS and Wafer Level Packaging Applications

Ha-Duong Ngo, André Hiess, V. Seidemann et al. · Journal of Physics Conference Series · 2006 · 23 citations · Full text

Electrical Engineering, Wafer Scale Processing, Engineering +14

Demonstration of a graphene-base heterojunction transistor with saturated output current

C. Strobel, Carlos Alvarado Chavarin, B. Leszczynska et al. · Journal of Applied Physics · 2019 · 11 citations

Graphene Nanomeshes, Electrical Engineering, Graphene Quantum Dot +10

Anisotropic Etching of Pyramidal Silica Reliefs with Metal Masks and Hydrofluoric Acid

Robert Kirchner, Volker Neumann, Felix Winkler et al. · Small · 2020 · 10 citations · Full text

Materials Engineering, Materials Science, Pyramidal Structures +15