Hardware Evaluation of the AES Finalists.

Abstract

This report describes our evaluation results of implementing hardware of the AES finalists, concentrating on 128-bit key version, using Mitsubishi Electric’s 0.35 micron CMOS ASIC design library. Our goal is to estimate the “critical path length” of data encryption /decryption logic and key setup time of key scheduling logic for each algorithm, which corresponds to the fastest possible encryption speed in feedback modes of operation such as CBC etc. To achieve this, we wrote fully loop-unrolled codes in VerilogHDL language without introducing pipeline structure that blocks the feedback.