Microarchitectural Timing Analysis is a formal analytical method within worst-case execution time analysis that characterizes the timing effects of low-level hardware structures and behaviors, distinguishing itself by focusing on architectural features such as caches, pipelines, and branch predictors to derive execution time bounds.
536
Publications
33.3K
Citations
1.2K
Authors
310
Institutions
Publications per year
2017–2026
58
Publications
536
Sheng Li, Jung Ho Ahn, Richard Strong et al. · 2009 · 2.4K citations
John Gibbon, Russell M. Church, Warren H. Meck · Annals of the New York Academy of Sciences · 1984 · 1.8K citations
1–5 of 536
Authors
1.2K
- FJ
17
h-index
- JA
16
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- EQ
16
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- LK
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- AR
14
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1–5 of 1.2K
Institutions
310
Intel (United States)
Santa Clara, United States
19 h-index
57 publications
3.9K citations
National University of Singapore
Singapore, Singapore
18 h-index
51 publications
4.6K citations
University of York
York, United Kingdom
17 h-index
44 publications
1.7K citations
Universitat Politècnica de Catalunya
Barcelona, Spain
17 h-index
98 publications
2.9K citations
Barcelona Supercomputing Center
Barcelona, Spain
16 h-index
86 publications
2.5K citations
Saarland University
Saarbrücken, Germany
16 h-index
35 publications
5.8K citations
Consejo Superior de Investigaciones Científicas
Madrid, Spain
15 h-index
23 publications
718 citations
North Carolina State University
Raleigh, United States
14 h-index
43 publications
3.3K citations
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Venues
- DROPS (Schloss Dagstuhl – Leibniz Center for Informatics)
Repository · 16 publications · 465 citations
14
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- ACM SIGARCH Computer Architecture News
12 publications · 2.1K citations
12
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- Real-Time Systems
11 publications · 363 citations
11
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- IEEE Micro
10 publications · 1.5K citations
10
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- Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013
Conference · 8 publications · 199 citations
8
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