Exploring manufacturability of novel 2D channel materials: 300 mm wafer-scale 2D NMOS & PMOS using MoS₂, WS₂, & WSe₂

Abstract

Rapid progress in fundamental understanding and development of 2D channel materials has yielded significant advances in contact resistance, gate oxide quality, and channel mobility, revealing opportunities for the future of Moore’s Law using highly-scaled 2D CMOS. We now scale up to 300 mm, for the first time, both NMOS and PMOS 2D transistors using today’s leading TMD candidates: MoS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> , WS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> , and WSe <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> . Our MoS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> outperforms WS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> as NMOS transistor due to higher mobility and lower contact resistance. WSe <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> multi-layers show high PMOS on-currents up to 200 μA/μm for larger grain size films. Larger TMD grain sizes outperform smaller grains for both NMOS and PMOS with up to 10× higher on-currents and steeper SS, identifying single crystal mono-layer channel uniformity as a paramount obstacle toward performance enhancement and reduced variation.