Journal of VLSI Circuits and Systems · 2023 · 29 citations · 10 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsComputer ArchitectureVlsi DesignDigital Integrated Circuit DesignDigital Integrated CircuitsField-programmable Gate Array ArchitectureFpga ArchitectureLow-power Digital Circuit DesignLow-power Fpga DesignAccuracyAnalog-to-digital Converter DesignComparator DesignDigital Circuit OptimizationDigital Signal Processing Block ArchitectureDigital Signal Processing BlocksLow-power Design For TestabilityVlsi Implementation
The creation of an 8-bit SAR ADC with a 0.8V and 5V input voltage is discussed in the publication. Cadence Virtuoso software was used to implement the design, which made use of both 180nm and 90nm technology. The comparator block, which was created using Verilog code and required to operate properly, was the main emphasis of the design. Since the comparator is the block that uses the most power overall, optimising it took up a sizable chunk of the design process. The DAC sub-block was implemented using an MDAC network to increase the ADC's accuracy. The ADC was driven by asynchronous control logic, which was implemented using Verilog code and did not require a clock signal.
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A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS
Yan Zhu, Chi‐Hang Chan, U-Fat Chio et al. · IEEE Journal of Solid-State Circuits · 2010 · 713 citations
Engineering, Computer Engineering, Electrical Engineering +17