2023 · 11 citations · 12 references
ComputingComputer EngineeringComputer ScienceComputer ArchitectureEdge ComputingLow-power DesignData CompressionEdge Data ProcessingEdge DevicesCmos ScalingEnergy ConsumptionEnergy-efficient Edge ComputingEnergy-efficient Hardware AccelerationEnergy-efficient ProcessingLow-complexity Compression AlgorithmsModel Compression
Recently, the edge-device DNN training has become of high importance, while the computation and access energy consumption of are too large. This paper proposes a CPE (Compress Process Element) with three characteristics. Firstly, CPE has a method of Reordering and Reusing Data (RRD) by controlling the output to reorder data. Secondly, CPE owns a Multi-directional Redundant Skip (MRS) mechanism, which anticipates all zeros and duplicate fields in advance. Thirdly, CPE contains a scheme to transform The Calculation Format (TCF), which transforms the input into another form. Evaluated with 28nm CMOS process, using CPE achieves 2.02 × energy reduction and offer 1.73 × speed up outperforming state-of-the-art trainable processor GANPU.
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Paulius Micikevicius, Sharan Narang, Jonah Alben et al. · arXiv (Cornell University) · 2017 · 881 citations · Full text
Brandon Reagen, Paul N. Whatmough, Robert Adolf et al. · ACM SIGARCH Computer Architecture News · 2016 · 471 citations
1.1 Deep Learning Hardware: Past, Present, and Future
Yann LeCun · 2019 · 191 citations