Extremely Large 3.5D Heterogeneous Integration for the Next-Generation Packaging Technology

Abstract

2.5D silicon interposer for multi-die heterogeneous integration is the mainstream package architecture for a high- performance computing (HPC) and an artificial intelligence (AI) application. In this study, 3.5D package is demonstrated to combine 2.5D silicon interposer and 3D architecture to obtain high-performance and high-density interconnection with the small footprint system package. Extremely large Si interposer (4x reticle size) was manufactured and integrated with multi logic test chips with 12-HBMs, 3-chiplets and 3D-ASIC. 3D-ASIC was manufactured by vertical interconnection of two partitioned chips by Cu-Cu hybrid bonding. 3D-ASIC will be able to overcome effectively the single chip reticle size limitation and large die yield issue in Si fabrication. Furthermore 12-HBMs and 3-chiplets were assembled on silicon interposer using Chip on Wafer (CoW) process for higher system bandwidth. 3D-ASIC was attached on silicon interposer by solder reflow bonding process with 40um bump pitch. To avoid underfill void on narrow chip gap and die to die space, vacuum devoid process was introduced and the underfill void under multi-chip was completely removed. The extremely large molded Si interposer with multi-die was assembled on organic substrate successfully showing the reliable joint quality by controlling molded Si interposer and substrate warpage effectively. The interfacial stress between various multi-heterogeneous chips was analyzed through finite element method (FEM) simulation and the impact on reliability will be discussed.