Novel Cell Architectures with Back-side Transistor Contacts for Scaling and Performance

Abstract

PowerVia increases the efficiency of power delivery by adding back-side interconnects [1]. It also improves performance by relaxing the minimum front-side interconnect pitch and by optimizing them for signaling. Research to further improve performance and density synergistically with PowerVia includes back-side device contacts and device stacking. In this paper, we present an experimental demonstration of a novel cell architecture with back-side device contacts and back side power delivery. Keywords: back-side power delivery, back-side contacts, BSCON.