Power-efficient Interconnects
Power-Efficient Interconnects is an interconnect architecture designed to minimize energy consumption during data transmission while maintaining performance and scalability, distinguishing itself from conventional interconnects through optimized signaling, routing, and circuit-level techniques that reduce dynamic and static power dissipation.
232
Publications
9.3K
Citations
799
Authors
211
Institutions
Publications per year
2017–2026
37
Parents
232
A 5-GHz Mesh Interconnect for a Teraflops Processor
Yatin Hoskote, Sriram Vangal, A. Singh et al. · IEEE Micro · 2007 · 531 citations
A 5-GHz Mesh Interconnect for a Teraflops Processor
Yatin Hoskote, Sriram Vangal, A. Singh et al. · IEEE Micro · 2007 · 518 citations
Fahad R. Dogar, Peter Steenkiste, Konstantina Papagiannaki · 2010 · 172 citations
1–5 of 232
799
8
h-index
6
h-index
5
h-index
5
h-index
5
h-index
1–5 of 799
211
Intel (United States)
Santa Clara, United States
15 h-index
73 publications
6K citations
Princeton University
Princeton, United States
11 h-index
31 publications
2.9K citations
University of Michigan
Ann Arbor, United States
10 h-index
48 publications
1.4K citations

Pennsylvania State University
State College, United States
6 h-index
16 publications
640 citations
Columbia University
New York, United States
6 h-index
25 publications
1.5K citations

University of Rochester
Rochester, United States
6 h-index
14 publications
228 citations
Texas A&M University
College Station, United States
6 h-index
20 publications
519 citations
IBM (United States)
Armonk, United States
5 h-index
34 publications
615 citations
1–8 of 211
9 publications · 399 citations
9
h-index
8 publications · 1.4K citations
8
h-index
5 publications · 190 citations
5
h-index
5 publications · 171 citations
5
h-index
4 publications · 276 citations
4
h-index
1–5