Power-efficient Interconnects

Power-Efficient Interconnects is an interconnect architecture designed to minimize energy consumption during data transmission while maintaining performance and scalability, distinguishing itself from conventional interconnects through optimized signaling, routing, and circuit-level techniques that reduce dynamic and static power dissipation.

232

Publications

9.3K

Citations

799

Authors

211

Institutions

Publications per year

2017–2026

37

Authors

799

  1. LP
    Li-Shiuan Peh

    Princeton University, United States

    8 publications · 870 citations

    8

    h-index

  2. DB
    David Blaauw

    University of Michigan, United States

    6 publications · 82 citations

    6

    h-index

  3. SB
    Shekhar Borkar

    Intel (United States), United States

    5 publications · 1.1K citations

    5

    h-index

  4. KB
    Keren Bergman

    Columbia University, United States

    5 publications · 296 citations

    5

    h-index

  5. RK
    Ram Krishnamurthy

    Intel (United States), United States

    5 publications · 78 citations

    5

    h-index

1–5 of 799

Venues

  1. IEEE Journal of Solid-State Circuits

    9 publications · 399 citations

    9

    h-index

  2. IEEE Micro

    8 publications · 1.4K citations

    8

    h-index

  3. 5

    h-index

  4. 5

    h-index

  5. IEEE Transactions on Computers

    4 publications · 276 citations

    4

    h-index

1–5