Trimmed-TDL-Based TDC Architecture for Time-of-Flight Measurements Tested on a Cyclone V FPGA

Abstract

This paper introduces a Trimmed-Tapped-Delay-Line-based Time-to-Digital Converter (TTDL-TDC) architecture. Unlike state-of-the-art works, where the propagation time of the TDL is roughly equivalent to the system clock period, the TDL of the proposed architecture can be shortened to use only 63% of the necessary length to propagate a clock cycle without loss of resolution. To achieve this reduction, the clock signal is propagated throughout this Trimmed TDL (TTDL), capturing its position with the rising edge of a latching signal. An encoder based on transition detectors and ones-counters modules is employed to determine the clock’s phase from the captured code in TTDL. The architecture was implemented in a Cyclone V FPGA, nevertheless, the proposed design methodology allows for migrating the design to any other FPGA device. The experimental results showed a resolution (LSB) of 5.98 ps and a overall precision of 7.6 ps. Additionally, the proposed design strategy saves hardware resources, allowing the exploration of multichannel measurement systems in low-end devices.