Timing Architecture

Timing Architecture is a formal computational framework within field-programmable gate array architecture that specifies the structural and operational principles governing signal propagation delays and clocking mechanisms to ensure precise temporal coordination of logic elements and interconnects.

116

Publications

4.6K

Citations

474

Authors

167

Institutions

Publications per year

2017–2026

21

Authors

474

  1. FL
    Fabrizio Lombardi

    Northeastern University, United States

    3 publications · 342 citations

    3

    h-index

  2. TC
    Ta-Shun Chu

    National Tsing Hua University, Taiwan

    3 publications · 170 citations

    3

    h-index

  3. MO
    Marco Ottavi

    University of Rome Tor Vergata, Italy

    3 publications · 342 citations

    3

    h-index

  4. MH
    Mark Horowitz

    Stanford University, United States

    3 publications · 215 citations

    3

    h-index

  5. TE
    Ted E. Williams

    Stanford University, United States

    3 publications · 329 citations

    3

    h-index

1–5 of 474

Venues

  1. IEEE Transactions on Nuclear Science

    9 publications · 341 citations

    9

    h-index

  2. IEEE Journal of Solid-State Circuits

    8 publications · 805 citations

    8

    h-index

  3. 7

    h-index

  4. 4

    h-index

  5. Journal of Instrumentation

    JINST · 4 publications · 122 citations

    4

    h-index

1–5