A Fully Fledged TDC Implemented in Field-Programmable Gate Arrays

TLDR

The study implements a fully fledged FPGA‑based time‑to‑digital converter on Xilinx XC4VFX60 FPGAs, incorporating self‑test, temperature‑variation compensation, and trigger‑matching. Self‑test uses statistical methods to measure delay‑chain resolution across 30–60 °C, enabling temperature compensation and INL calibration, while trigger‑matching is achieved with a content‑addressable memory that programs trigger‑latency and matching window. After compensation and INL calibration, the TDC achieves an RMS time‑measurement error below 30 ps per channel and a resolution of about 50 ps, with effective trigger‑matching via the CA memory.

Abstract

The motivation of this paper is to implement a fully fledged FPGA-Based TDC in XILINX XC4VFX60 FPGAs, with the features of Self-Test, temperature variation compensation and trigger-matching. Self-Test is performed with the statistical methods and gives the resolution of delay chain at its temperature and supplied voltage. The resolution changes with the environment temperature, and the corresponding value was recorded by Self-Test from 30∼60 °C for compensation. After compensation and INL calibration, the RMS of time measurement remains less than 30 ps per channel of the total six, and the resolution is about 50 ps. Trigger-matching is implemented using content addressable memory with the two parameters: trigger-latency and matching window programmable.