High‐Performance CMOS Inverter Array with Monolithic 3D Architecture Based on CVD‐Grown n‐MoS₂ and p‐MoTe₂

Abstract

Abstract In this work, monolithic three‐dimensional complementary metal oxide semiconductor (CMOS) inverter array has been fabricated, based on large‐scale n‐MoS 2 and p‐MoTe 2 grown by the chemical vapor deposition method. In the CMOS device, the n‐ and p‐channel field‐effect transistors (FETs) stack vertically and share the same gate electrode. High k HfO 2 is used as the gate dielectric. An Al 2 O 3 seed layer is used to protect the MoS 2 from heavily n‐doping in the later‐on atomic layer deposition process. P‐MoTe 2 FET is intentionally designed as the upper layer. Because p‐doping of MoTe 2 results from oxygen and water in the air, this design can guarantee a higher hole density of MoTe 2 . An HfO 2 capping layer is employed to further balance the transfer curves of n‐ and p‐channel FETs and improve the performance of the inverter. The typical gain and power consumption of the CMOS devices are about 4.2 and 0.11 nW, respectively, at V DD of 1 V. The statistical results show that the CMOS array is with high device yield (60%) and an average voltage gain value of about 3.6 at V DD of 1 V. This work demonstrates the advantage of two‐dimensional semi‐conductive transition metal dichalcogenides in fabricating high‐density integrated circuits.