Vertical Channel-All-Around (CAA) IGZO FET under 50 nm CD with High Read Current of 32.8 μA/μm (V_th + 1 V), Well-performed Thermal Stability up to 120 ℃ for Low Latency, High-density 2T0C 3D DRAM Application

Abstract

For the first time, vertical channel-all-around (CAA) IGZO FET is scaled down to an active footprint of less than 50×50 nm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . With optimized IGZO thickness (~3 nm) and high-K dielectric (HfO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf> ), high current density of 32.8 μA/μm at V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> +1 V with subthreshold swing of 92 mV/dec is achieved in the IGZO CAA FET with channel length of 55 nm and critical dimension (CD) of 50 nm. Good thermal stability and reliability is also demonstrated by temperature variation tests and positive-bias-temperature-stress (PBTS) from -40 ℃ to 120 ℃. Our results show that CAA IGZO FET is a promising candidate for the high-density, high-performance 3D DRAM beyond 1α nodes in the future.