2015 2nd International Conference on Electronics and Communication Systems (ICECS) · 2015 · 11 citations · 11 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsVlsi DesignLeakage Power ReductionMemory Subsystem DesignPower ManagementLeakageLeakage Current ReductionLeakage PowerLeakage Power OptimizationMemory Circuit DesignNon-volatile Memory DesignPower-efficient Memory DesignStatic Random-access Memory Design
In this paper, we design different type of SRAM cells. This paper compares the performance of five SRAM cell topologies, which include the conventional 6T, 7T, 8T, 9T and the 10T SRAM cell implementations. In particular, the leakage currents, leakage power and read behaviour of each SRAM cells are examined. In 10T SRAM cell implementation results, reduced leakage power and leakage current by 36% and 64% respectively, the read stability is increased by 13% over conventional 6T, 7T, 8T and 9T SRAM cells. As a result, the 10T SRAM always consumes lowest leakage power and leakage current; improve read stability as compared to the 6T, 7T, 8T and 9T SRAM cells. The aim of this paper is to reduce the leakage power, leakage current and improve the read behaviour of the different SRAM cell structures using cadence tool at 45nm technology while keeping the read and write access time and the power as low as possible.
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Drowsy caches: simple techniques for reducing leakage power
Krisztián Flautner, Nam Sung Kim, Steve Martin et al. · 2003 · 347 citations