A 14 Bit 1 GS/s RF Sampling Pipelined ADC With Background Calibration

Abstract

We discuss a 14 bit 1 GS/s RF sampling pipelined ADC that utilizes correlation-based background calibration to correct the inter-stage gain, settling and memory errors. To improve the sampling linearity and RF sampling performance, the ADC employs input distortion cancellation and a digital background calibration technique to compensate for the non-linear charge injection (kick-back) from the sampling capacitors on the input driver. In addition, an effective dithering technique is embedded in the calibration signal to break the dependence of the calibration's convergence on the input signal amplitude. The ADC is fabricated on a 65 nm CMOS process and has an integrated input buffer. With a 140 MHz and 2 Vpp input signal, the SNR is 69 dB, the SFDR is 86 dB, and the power is 1.2 W.