A 12-Bit 3 GS/s Pipeline ADC With 0.4 mm$^{2}$ and 500 mW in 40 nm Digital CMOS

Abstract

A 12-bit 3 GS/s 40 nm two-way time-interleaved pipeline analog-to-digital converter (ADC) is presented. The proposed adaptive power/ground architecture eliminates the headroom limitations due to the deeply scaled power supply in nanometer CMOS technologies, while preserving the intrinsic speed of thin-oxide MOSFETs with minimum channel length for key analog blocks. Moreover, in terms of the signal swing, the proposed reference extrapolation scheme offers a smooth transition between the multiplying digital-to-analog converter stages and the last flash stage. With these two techniques, the ADC achieves a SNR of 61 dB and a DNL of -0.5/+0.5 LSB, while consuming 500 mW at a 3 GS/s sampling rate and occupying an area of 0.4 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in 40 nm CMOS process.