28nm CIS-Compatible Embedded STT-MRAM for Frame Buffer Memory

Abstract

We demonstrate embedded STT-MRAM fully integrated onto 28nm CIS logic platform, highlighting the world-best macro density of 13.94 Mb/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The macro provides 55% area saving over 28nm SRAM. The MTJ processes are compatible with standard 3D-stacked CIS integration processes that require sufficient 400°C heat budget. The MTJ stack has also been improved for frame buffer applications, achieving write speed <50ns and endurance >1E10 cycles. Furthermore, we have confirmed scalability of the CIS-compatible MTJ processes beyond 28nm. With advanced MTJ patterning processes, we have verified that MTJ short failure rate can be suppressed below 1ppm even at a 40% smaller pitch as compared to the current MTJ pitch at 28nm. This result reveals that our frame-buffer STT-MRAM technology is scalable to 14nm FinFET node.