A 5-nm 254-TOPS/W 221-TOPS/mm² Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations

Abstract

Computing-in-memory (CIM) is being widely explored to minimize power consumption in data movement and multiply-and-accumulate (MAC) for edge-AI devices. Although most prior work focuses on analog-based CIM (ACIM) to leverage the BL charge/discharge operation, the lack of accuracy caused by transistor variation and the ADC is an issue [1]–[3]. In contrast, a digital-based CIM (DCIM) approach realizes enough accuracy and flexibility for various input and weight bit widths [4], while also benefiting from technology scaling. This paper proposes a 64kb DCIM macro using a one-read and one-write (1R1W) 12T bitcell. The DCIM macro can realize simultaneous MAC + write operations and wide range dynamic voltage-frequency scaling (DVFS) due to the 12T cell's 1R1W functionality and low-voltage operation. Further improvements in power-performance-area (PPA) are obtained by optimizing the circuit architecture and layout topology.