IEEE Journal of Solid-State Circuits · 1995 · 28 citations · 5 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignSystem-on-chip DesignCmos Circuit DesignDigital Logic DesignHigh-frequency Power ConversionLow-power Digital Circuit DesignBus ArchitectureCmos Logic CircuitsCmos Logic DesignComplementary Metal-oxide-semiconductor LogicConfigurable Bus ArchitectureLow-power Logic DesignLow-voltage Cmos DesignUltra-low-power Cmos
A reduced-swing internal bus scheme is proposed for achieving ultralow-power LSI's. The proposed data-dependent logic swing bus (DDL bus) uses charge sharing between bus wires and an additional bus wire to reduce its voltage swing. With this technique, the power dissipation of the proposed bus is reduced to 1/16 that of a conventional bus when used for a 16-b-wide bus. In addition, a dual-reference sense-amplifying receiver (DRSA receiver) has been developed to convert a reduced-swing bus signal to a CMOS-level signal without loss of noise margin or speed. Experimental circuits fabricated using 0.5-/spl mu/m CMOS process verify the low-power operation of the proposed bus at an operating frequency of 40 MHz with a supply voltage of 3.3 V.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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An experimental 1.5-V 64-Mb DRAM
Y. Nakagome, Hiroki Tanaka, Kazuhiro Takeuchi et al. · IEEE Journal of Solid-State Circuits · 1991 · 182 citations
Engineering, Computer Engineering, Electrical Engineering +17
Sub-1-V swing bus architecture for future low-power ULSIs
Y. Nakagome, K. Itoh, M. Isoda et al. · 2003 · 29 citations
Engineering, Computer Engineering, Electrical Engineering +17
A 16 b low-power-consumption digital signal processor
Katsuhiko Ueda, Toshio Sugimura, Michio Okamoto et al. · 1993 · 14 citations
Engineering, Computer Engineering, Electrical Engineering +17