Effects of Bias Temperature Stress and Irradiation in Commercial p-Channel Power VDMOS Transistors

Abstract

The effects of bias temperature stress and irradiation in commercial p-channel power VDMOS transistors were investigated. In order to additionally elucidate the effects that take place in these power devices during the irradiation after the NBT stress, the relative contributions of gate oxide charge <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\Delta V_{ot}/\Delta V_{\text{TH}})$</tex> and interface traps <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\Delta V_{\mathrm{i}\mathrm{t}}/\Delta V_{\text{TH}})$</tex> to the threshold voltage shifts are presented and analyzed. It was found that in the case of irradiation without gate voltage the duration of the preirradiation NBT stress had a more pronounced impact on the radiation response of power VDMOS transistors, and that the contribution of the oxide trapped charge plays a more pronounced role in components previously NBT stressed for 1 hour than in those stressed for 1 week.