2009 · 15 citations · 12 references
ComputingComputer EngineeringComputer ScienceAlgorithmsDesign AutomationFormal MethodsDeductive VerificationEquivalence CheckingRedundancy TechniquesSequential Logic DescriptionVerificationHardware Equivalence CheckingInductive Proof TechniquesSequential Circuit SynthesisSequential Equivalence CheckingSequential Logic Synthesis
The process of sequential redundancy identification is the cornerstone of sequential synthesis and equivalence checking frameworks. The scalability of the proof obligations inherent in redundancy identification hinges not only upon the ability to cross-assume those redundancies, but also upon the way in which these assumptions are leveraged. In this paper, we study the technique of speculative reduction for efficiently modeling redundancy assumptions. We provide theoretical and experimental evidence to demonstrate that speculative reduction is fundamental to the scalability of the redundancy identification process under various proof techniques. We also propose several techniques to speed up induction-based redundancy identification. Experiments demonstrate the effectiveness of our techniques in enabling substantially faster redundancy identification, up to six orders of magnitude on large designs.
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Scalable and scalably-verifiable sequential synthesis
Alan Mishchenko, Michael Case, Robert K. Brayton et al. · 2008 · 47 citations