Hardware Equivalence Checking
Hardware Equivalence Checking is a formal verification method that belongs to the class of equivalence checking techniques, specifically designed to determine whether two hardware designs exhibit identical input-output behavior under all permissible operating conditions.
141
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5K
Citations
314
Authors
116
Institutions
Publications per year
2017–2026
12
Parents
141
Symbolic model checking using SAT procedures instead of BDDs
Armin Biere, Alessandro Cimatti, E. M. Clarke et al. · 1999 · 697 citations
Formal verification of a pipelined microprocessor
Mandayam Srivas, Mark Bickford · IEEE Software · 1990 · 118 citations
Challenges and Trends in Modern SoC Design Verification
Wen Chen, Sandip Ray, Jayanta Bhadra et al. · IEEE Design and Test · 2017 · 107 citations
1–5 of 141
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University of California, Santa Barbara, United States
6 publications · 148 citations
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1–5 of 314
116
Carnegie Mellon University
Pittsburgh, United States
8 h-index
19 publications
3K citations
Intel (United States)
Santa Clara, United States
7 h-index
10 publications
190 citations
University of California, Santa Barbara
Santa Barbara, United States
7 h-index
11 publications
350 citations
Fujitsu (United States)
Sunnyvale, United States
7 h-index
7 publications
1K citations
The University of Texas at Austin
Austin, United States
6 h-index
9 publications
200 citations
IBM Research - Thomas J. Watson Research Center
Yorktown Heights, United States
6 h-index
10 publications
546 citations

Concordia University
Montreal, Canada
5 h-index
8 publications
133 citations
University of Bremen
Bremen, Germany
5 h-index
8 publications
313 citations
1–8 of 116
9 publications · 348 citations
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Conference · 4 publications · 86 citations
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4 publications · 101 citations
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ICCAD · 3 publications · 91 citations
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3 publications · 59 citations
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