Hardware Equivalence Checking

Hardware Equivalence Checking is a formal verification method that belongs to the class of equivalence checking techniques, specifically designed to determine whether two hardware designs exhibit identical input-output behavior under all permissible operating conditions.

141

Publications

5K

Citations

314

Authors

116

Institutions

Publications per year

2017–2026

12

Authors

314

  1. KC
    Kwang‐Ting Cheng

    University of California, Santa Barbara, United States

    6 publications · 148 citations

    6

    h-index

  2. SR
    Sandip Ray

    University of Florida, United States

    6 publications · 207 citations

    6

    h-index

  3. MF
    Masahiro Fujita

    The University of Tokyo, Japan

    5 publications · 786 citations

    5

    h-index

  4. MS
    Magdy S. Abadir

    University of California, Santa Barbara, United States

    5 publications · 228 citations

    5

    h-index

  5. KH
    Kecheng Hao

    Portland State University, United States

    5 publications · 100 citations

    5

    h-index

1–5 of 314

Venues

  1. 9

    h-index

  2. International Conference on Computer Aided Design

    Conference · 4 publications · 86 citations

    4

    h-index

  3. 4

    h-index

  4. 3

    h-index

  5. IEEE Design & Test of Computers

    3 publications · 59 citations

    3

    h-index

1–5