Sequential Equivalence Checking

Sequential Equivalence Checking is a formal verification method that belongs to the class of equivalence checking techniques, distinguished by its focus on proving the behavioral equivalence of two sequential circuits or systems across all clock cycles, accounting for temporal dynamics and state retention elements.

65

Publications

1.9K

Citations

127

Authors

46

Institutions

Publications per year

2017–2026

2

Authors

127

  1. KC
    Kwang‐Ting Cheng

    University of California, Santa Barbara, United States

    7 publications · 212 citations

    7

    h-index

  2. RK
    Robert K. Brayton

    University of California, Berkeley, United States

    6 publications · 106 citations

    6

    h-index

  3. KC
    Kuang-Chien Chen

    University of California, Santa Barbara, United States

    5 publications · 151 citations

    5

    h-index

  4. AR
    A. Richard Newton

    University of California, Berkeley, United States

    4 publications · 134 citations

    4

    h-index

  5. SH
    Shi‐Yu Huang

    National Tsing Hua University, Taiwan

    4 publications · 104 citations

    4

    h-index

1–5 of 127

Venues

  1. 8

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  2. 2

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  3. 2

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  4. IEEE Transactions on Computers

    2 publications · 58 citations

    2

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  5. IEEE Design & Test of Computers

    2 publications · 54 citations

    2

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1–5