Sequential Equivalence Checking
Sequential Equivalence Checking is a formal verification method that belongs to the class of equivalence checking techniques, distinguished by its focus on proving the behavioral equivalence of two sequential circuits or systems across all clock cycles, accounting for temporal dynamics and state retention elements.
65
Publications
1.9K
Citations
127
Authors
46
Institutions
Publications per year
2017–2026
2
Parents
65
1–5 of 65
127
University of California, Santa Barbara, United States
7 publications · 212 citations
7
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6
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University of California, Santa Barbara, United States
5 publications · 151 citations
5
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4
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4
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1–5 of 127
46
University of California, Berkeley
Berkeley, United States
10 h-index
24 publications
607 citations
University of California, Santa Barbara
Santa Barbara, United States
7 h-index
15 publications
496 citations
Intel (United States)
Santa Clara, United States
4 h-index
8 publications
120 citations
The University of Texas at Austin
Austin, United States
4 h-index
8 publications
164 citations
Fujitsu (United States)
Sunnyvale, United States
3 h-index
3 publications
83 citations
University of Bremen
Bremen, Germany
3 h-index
7 publications
243 citations
Eindhoven University of Technology
Eindhoven, The Netherlands
3 h-index
3 publications
221 citations
IBM (United States)
Armonk, United States
3 h-index
12 publications
454 citations
1–8 of 46
8 publications · 400 citations
8
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2 publications · 42 citations
2
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Conference · 2 publications · 87 citations
2
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2 publications · 58 citations
2
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2 publications · 54 citations
2
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