A Novel Insight on Interface Traps Density (Dit) Extraction in GaN-on-Si MOS-c HEMTs

Abstract

This paper aims to investigate the interface traps density (Dit) extraction on MOS gate stacks processed on GaN-on-Si substrates. CGV (Capacitance-Conductance) measurements under different frequencies (f = 1kHz-1MHz) and temperatures (T = 20K-500K) on various Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /UID-GaN MOS capacitors were carried out. Thorough analysis under dark and UV light compared to TCAD/analytical modeling reveal a strong distributed series resistance under the gate related to the high resistivity of UID-GaN layer. This effect leads to an overestimation of the actual Dit value extracted at high frequencies (> 10kHz). Choosing an adequate doping under the gate (n-type) cancels the series resistance effect and unlocks a reliable extraction through {T/f} dependent CGV measurements.