Sources of variability in scaled MoS₂ FETs

Abstract

Through advances in growth, cleaning, and device fabrication, our scaled MoS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> FET flow has reached sufficient maturity to study variability. We show devices with median SS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</inf> 80mV/dec and I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</inf> >100µA/µm and find that thinning down the MoS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> channel from three to one layer results in strongly reduced SS and V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> variability, despite the presence of second layer MoS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> crystals. The scaling of σV <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> with device dimensions of the thin-channel MoS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> FETs with EOT=2.6nm is found nearly on par with state-of-the-art Si finFETs at EOT=0.8nm, with a Pelgrom slope of A <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vt</inf> =2.8mV.µm. Finally, by directly correlating physical characterization, electrical measurements and 3D TCAD simulations, we identify second layer islands as a significant contributor to SS degradation and variability.