Dual gate synthetic WS₂ MOSFETs with 120μS/μm Gm 2.7μF/cm² capacitance and ambipolar channel

Abstract

We have engineered dual gate WS2 transistors with scaled top and back gate stacks based on a surface physisorption ALD approach for advanced logic applications. Connected dual gate MOSFET operation with a 2ML WS2 channel reaches 210μA/um drain current and 2.7μF/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> capacitance (>3.4×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">13</sup> /cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> sheet charge density) at 3V gate bias, with >10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> on-off ratio, 120μS/um max. transconductance and 109mV/dec sub-threshold swing at 100nm Lch. This dual gate design enables us to explore EOT scaling, ambipolar I-V and C-V(capacitance-voltage) response on CVD WS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> channel.