Ensuring Cryptography Chips Security by Preventing Scan-Based Side-Channel Attacks With Improved DFT Architecture

Abstract

Cryptography chips are often used in some applications, such as smart grids and Internet of Things (IoT) to ensure their security. Cryptographic chips must be strictly tested to guarantee the correctness of the encryption and decryption. Scan-based design-for-testability (DFT) provides high test quality. However, it can also be misused to steal the cipher key of cryptographic chips by hackers. In this article, we present a new scan design methodology that can resist scan-based side-channel attacks by the dynamical obfuscation of scan input data and scan output data. The scan test is managed by a test password, which consists of load password and scan password. When the chip enters into the test mode, it is required to apply the test password via some external input ports. Once the correct load password is delivered, the scan password can be loaded into a special shift register. If the scan password is also correct, the chip testing can proceed normally. In case the load password or the scan password is wrong, the data in scan chains cannot be propagated correctly. Specifically, some elusory bits are sneaked into scan chains dynamically. The advantage of the proposed method is that it has no negative impact on design performance and test flow when powerfully protecting cryptographic chips. The area penalty is also acceptably low compared with other schemes.