IEEE Solid-State Circuits Letters · 2020 · 31 citations · 10 references
EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsClock Distribution NetworksClock ManagementCmos Circuit DesignJitter AnalysisMixed-signal Integrated Circuit DesignNoise In Analog CircuitsCircuit EvaluationJitter CompensationJitter MitigationJitter SourcesPhase NoisePhase Noise AnalysisPhase-locked Loop DesignPhase-locked Loops
This letter presents a type-I narrow-pulse-sampling (NPS) phase-locked loop (PLL). It features a circuit technique: NPS phase detector + T-shape switch, to address the main spur-related nonidealities. Fabricated in 28-nm CMOS, the NPS-PLL operating at 3.3-GHz measures a -78.7-dBc reference spur and a -128.1-dBc/Hz absolute in-band phase noise at 1-MHz offset for a jitter-power figure-of-merit (FOM) of -254 dB, without the need of calibration and reference buffer.
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