Scaled transistors with 2D materials from the 300mm fab

Abstract

Integration of 2D-materials brings a new set of challenges to a 300 mm Si CMOS fab. We have opted for double gated WS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> transistors as test vehicle with transition metal dichalcogenides as channel. Moreover, we explore two different routes within a modified industry standard flow, differentiating in channel deposition method either by direct deposition or via layer transfer. The integration flow mitigates the constraints of high surface sensitivity and low adhesion for these materials. Device performance of I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</inf> /I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</inf> up to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> is achieved and WIW mapping is obtained opening the route for further process understanding.